Hybrid ridge waveguide

ABSTRACT

Embodiments of the invention relate to an electro-optic device comprising a first region of silicon semiconductor material and a second region of III-V semiconductor material. A waveguide of the optical device is formed in part by a ridge in the second region. An optical mode of the waveguide is laterally confined by the ridge of the second region and vertically confined by a vertical boundary included in the first region. The ridge structure further serves as a current confinement structure over the active region of the electro-optic device, eliminating the need for implantation or other structures that are known to present reliability problems during manufacturing. The lack of “voids” and implants in electro-optic devices according to embodiments of the invention leads to better device reliability, process repeatability and improved mechanical strength.

FIELD

Embodiments of the invention generally pertain to photonic circuits, andmore particularly to optical waveguides for hybrid photonic devicescomprising silicon and III-V semiconductor material.

BACKGROUND

Semiconductor photonic devices, such as lasers, have an active structurein which electrons and holes are converted into photons to produceoptical emissions. FIG. 1 illustrates a cross-sectional view of priorart semiconductor laser 100. When a positive electrode is connected top-type electrical contact 106 and negative electrodes are connected ton-type electrical contacts 112, and a voltage is applied, laser 100becomes forward biased. Electrical current (i.e., holes and electrons)is injected towards active layer 109. Holes in p-type region 108 move ina direction away from p-type electrical contact 106 toward n-typeelectrical contacts 112. Electrons in n-type layer 110 move in adirection away from n-type contacts 112 toward p-type electrical contact106. The active structure of laser 100 includes optical mode 113 and theportion of active layer 109 included in optical mode 113. As the holesand electrons meet at the active structure, the holes and electronscombine to emit light.

Regions 107 are implanted in order to inhibit electrical conduction andforce the electrical current to flow from p-type electrical contact 106through region 111 and into the portion of active layer 109 thatoverlaps optical mode 113. Implant regions 107 present reliabilityissues for device 100, as proton implanted regions cannot be too closeto the active region of the device due to concerns about implant damagecausing current to spread and leak outside of the confined area

The prior art laser of FIG. 1 further includes silicon waveguide 104formed on a silicon on insulator substrate that includes silicon toplayer 101, silicon dioxide layer 102 and silicon substrate 103. Siliconwaveguide 104 is formed by etched regions 105 included in silicon toplayer 101.

Etched regions 105 cause several detrimental effects for laser 100.Creating said regions results in voids in the structure that reduce themechanical strength of the device. These waveguide confinementstructures further result in the device having poor thermal performancedue to material loss where the material was etched away to form regions105. The areas that heat may dissipate away from the laser's activeregion are also restricted due to regions 105 and layer 102. Prior artsolutions to improve thermal performance have included creating thermalshunts in a lasing device, but this solution requires additionalprocessing steps.

BRIEF DESCRIPTION OF THE DRAWINGS

The following description includes discussion of figures havingillustrations given by way of example of implementations of embodimentsof the invention. The drawings should be understood by way of example,and not by way of limitation. As used herein, references to one or more“embodiments” are to be understood as describing a particular feature,structure, or characteristic included in at least one implementation ofthe invention. Thus, phrases such as “in one embodiment” or “in analternate embodiment” appearing herein describe various embodiments andimplementations of the invention, and do not necessarily all refer tothe same embodiment. However, they are also not necessarily mutuallyexclusive.

FIG. 1 is a block diagram of a prior art semiconductor laser.

FIG. 2 is a block diagram of an optical device according to anembodiment of the invention.

FIG. 3 is a block diagram of an optical device according to anembodiment of the invention.

FIG. 4 is a block diagram of an optical device including an alternativewaveguide confinement structure according to an embodiment of theinvention.

FIG. 5 is a block diagram of an optical device including an alternativewaveguide confinement structure according to an embodiment of theinvention.

FIG. 6 is a block diagram of a simplified optical system utilizingembodiments of the invention.

Descriptions of certain details and implementations follow, including adescription of the figures, which may depict some or all of theembodiments described below, as well as discussing other potentialembodiments or implementations of the inventive concepts presentedherein. An overview of embodiments of the invention is provided below,followed by a more detailed description with reference to the drawings.

DETAILED DESCRIPTION

Embodiments of the present invention relate to an electro-optic devicecomprising a first region of silicon semiconductor material and a secondregion of III-V semiconductor material, wherein a waveguide of thedevice is formed in part by a ridge in the second region. An opticalmode of the waveguide is laterally confined by the ridge of the secondregion and vertically confined by a vertical boundary included in thefirst region.

It will be understood in view of the example embodiments below thatincluding a ridge to function as a lateral waveguide confinement in theIII-V region of an electro-optic device, rather than creating voids inthe silicon region of the device, allows for greater contact areabetween the III-V and silicon regions, thereby leading to better thermalconductivity and heat extraction out of the device. The ridge structurefurther serves as a current confinement structure over the active regionof the electro-optic device, eliminating the need for implantation orother structures that are known to present reliability problems duringmanufacturing. The lack of “voids” and implants in electro-optic devicesaccording to embodiments of the invention leads to better devicereliability, process repeatability and improved mechanical strength.

FIG. 2 is a block diagram of an embodiment of the invention. It is to beunderstood that there exist various processing techniques that may beused to form the device as shown. Accordingly, the inventive structuresillustrated in this and the other figures described below may be formedusing any acceptable process sequence that yields the various deviceelements, element positions and associated doping levels required foracceptable operation.

In this embodiment, electro-optic device 200 includes a siliconsemiconductor slab including silicon top layer 201, vertical confinementlayer 202 and silicon substrate 203. It is to be understood that inalternative embodiments, substrate layer 203 may be a diamond substrate,a glass substrate, or any functional equivalent. Vertical confinementlayer 202 may be formed of any dielectric material suitable forconfining an optical mode (e.g., layer 201 may be a silicon dioxidelayer, a silicon nitride layer, or any functionally equivalentinsulating layer with a refractive index lower than silicon top layer201).

Device 200 further includes a III-V semiconductor slab including p-typelayer 208, active layer 209 and n-type layer 210 (thereby forming aP-I-N diode). The term “p-type layer,” as used herein, describes a layercomprising a material that has more positive carriers (i.e., holes) thannegative carriers (i.e., electrons). The term “n-type layer,” as usedherein, describes a layer comprising a material that has more negativecarriers than positive carriers.

In an alternative embodiment, layer 208 may be an n-type layer, andlayer 210 may be a p-type layer. In another alternative embodiment,layers 208 and 210 may be n-type layers, while active region 209 mayinclude a tunnel junction to convert n-type majority carriers to p-typemajority carriers. This alternative embodiment avoids the associatedoptical and microwave loss of p-type materials due to the use ofp-dopants.

III-V semiconductor materials have elements that are found in group IIIand group V of the periodic table (e.g., Indium Gallium ArsenidePhosphide (InGaAsP), Gallium Indium Arsenide Nitride (GaInAsN)). Thecarrier dispersion effects of III-V based materials may be significantlyhigher than in silicon based materials for bandgaps closer to thewavelength of the light being transmitted or modulated, as electronspeed in III-V semiconductors is much faster than that in silicon. Inaddition, III-V materials have a direct bandgap which is required forthe most efficient creation of light from electrical pumping. Thus,III-V semiconductor materials enable photonic operations with anincreased efficiency over silicon for both generating light andmodulating the refractive index of light.

Active layer 209 is of a III-V semiconductor with high electro-opticefficiency—i.e., the absorption coefficient (i.e., the imaginary portionof the complex refractive index) and the refractive index (i.e., thereal portion of the complex refractive index) of active layer 209 iseasily affected by either the Franz Kheldysh effect if active layer 209comprises bulk material (e.g., intrinsic Indium Gallium ArsenidePhosphide (i-InGaAsP) or Indium Aluminum Gallium Arsenide (InAlGaAs)) orthe Quantum Confined Stark Effect (QCSE) if active layer 209 comprisesmultiple quantum wells (MQW).

Optical waveguide 250 is formed by ridge 260 (which is “bolded” or“thicker” in the figure for illustrative purposes only), including ridgesides 261 and 262. It is clear that in this embodiment, waveguide 250 isformed by features in the III-V region of device 200 as opposed to beingformed by features in the silicon region of the device, as can be seenin FIG. 1, wherein waveguide 104 is formed by voids 105 included insilicon top region 101. Thus, the silicon and III-V regions of device200 have a greater contact area than devices in the prior art (e.g., inthis embodiment, layer 210 is continuously coupled to layer 201).

Overclad regions 207 may be formed on the device to improve mechanicalstability, and may be of any material used to form vertical confinementlayer 202 or any material with a lower refractive index than layer 208.Overclad regions 207 further provide vertical optical confinement andpassivation as described below. It is understood that the areas adjacentto ridge sides 261 and 262 provide optical confinement if left as voids(i.e., areas comprising air), but that forming overclad regions 207provides for mechanical stability in addition to optical confinement.

Thus, optical mode 213 is vertically confined by vertical confinementlayer 202, ridge 260 and overclad regions 207 while being laterallyconfined by ridge sides 261 and 262. Said ridge sides also confineinjection current from electrode 206 towards the portion of active layer209 that overlaps optical mode 213. Embodiments of the invention thuseliminate the need for the etched regions (e.g., etched regions 105 ofFIG. 1) and implanted regions (e.g., implant regions 107 of FIG. 1) ofthe prior art and reduce the associated reliability problems known inthe art.

It will be understood that the optical device of FIG. 2 may be used toamplify, modulate or detect light transmitted through the opticalwaveguide of the device by applying an electrical difference tocomplimentary electrodes 206 and 212 to either forward bias (i.e., foramplification) or reverse bias (i.e., for modulation or detection) thestructure. The complex refractive index (i.e., at least one of the realand the imaginary refractive index) of at least the portion of activelayer 209 included in optical mode 213 changes based on an electricaldifference (e.g., electrical voltage, electrical field) applied toelectrodes 206 and 212. These changes to the refractive index (orindexes) are proportional to the strength of the electrical differenceapplied to electrodes 206 and 212.

In this embodiment, electrodes 212 are coupled to n-type layer 210.Thus, it is to be understood that there is no electrical conductionthrough silicon top layer 201. In this embodiment, as opposed toembodiments where electrical conduction does occur through the silicontop layer of a device (see below), resistance is high as it determinedby thin layer 210; however, there are less processing steps needed tocreate device 200 and no conductive bond is required to couple thesilicon region with the III-V region (i.e., no conductive bond isrequired to couple layers 210 and 201).

FIG. 3 is a block diagram of an embodiment of the invention. In thisembodiment, electro-optic device 300 includes a silicon semiconductorslab including silicon top layer 301, vertical confinement layer 302 andsilicon substrate layer 303. It is to be understood that in alternativeembodiments, silicon substrate layer 303 may be a diamond substrate, aglass substrate, or any functional equivalent. Device 300 furtherincludes a III-V semiconductor slab including p-type layer 308, activelayer 309 and n-type layer 310.

In an alternative embodiment, layer 308 may be an n-type layer, andlayer 310 may be a p-type layer. In another alternative embodiment,layers 308 and 310 may be n-type layers, while active region 309 mayinclude a tunnel junction to convert n-type majority carriers to p-typemajority carriers.

Ridge 360 including sides 361 and 362 forms optical waveguide 350 andprovides lateral confinement for optical mode 313 (vertical confinementlayer 302, ridge 360 and overclad regions 307 provide verticalconfinement of said optical mode). Overclad regions 307 may be formed onthe device to improve mechanical stability, and may be of any materialused to form vertical confinement layer 302.

In this example embodiment, electrodes 312 are coupled to silicon toplayer 301 (as opposed to the example embodiment illustrated in FIG. 2,wherein electrodes 212 are coupled to III-V n-type layer 210). Thus, itis to be understood that electrical conduction occurs through bothn-type layer 310 and silicon top layer 301 when an electrical differenceis applied to electrodes 306 and 312. It is to be understood that thisexample arrangement allows for less resistance through layer 301 as itis thicker than n-type layer 210 of the embodiment illustrated in FIG.2. It is to be further understood the silicon top layer 301 will sufferless optical loss if it is doped for conduction and if a conductive bondis used to couple layers 301 and 310.

The ridges illustrated in FIGS. 2 and 3 are shown to be included only inthe top layers of the III-V semiconductor regions of their respectivedevices (i.e., ridges 260 and 360 are included only in p-type layers 208and 308 respectively). It is to be understood that these ridges are tobe viewed as examples only, and are not to limit the structure of ridgesin alternative embodiments of the invention. FIGS. 4 and 5 illustratealternative waveguide confinement structures according to embodiments ofthe invention. Device 400 of FIG. 4 is similar to device 200 of FIG. 2as described above, except sides 461 and 462 of ridge 460 formingoptical waveguide 450 extend through both p-type layer 408 and activelayer 409 (as described above, in other embodiments the layer “above”active layer 409 may be an n-type layer). Thus optical mode 413 islaterally confined by ridge sides 461 and 462 and vertical confined bylayer 202, and ridge sides 461 and 462 further confine the area in whichactive layer 409 receives current injected from electrode 206. Overcladregions 407 may further provide mechanical stability for device 400.

Device 500 of FIG. 5 is similar to device 300 of FIG. 3 as describedabove, except ridge sides 561 and 562 of ridge 560 forming opticalwaveguide 550 extend through the layers of the III-V region of thedevice—i.e., in this example p-type layer 508, active layer 509 andn-type layer 510 (the configuration of the layers of the III-V region ofthe device may differ in other embodiments as previously described).Thus optical mode 513 is laterally confined by ridge sides 561 and 562and vertical confined by layer 202, and ridge sides 561 and 562 furtherconfine the area in which the III-V semiconductor region of device 500(i.e., the areas that n-type layer 510 and active layer 509 may receivecurrent from electrodes 312 flowing through silicon top layer 301 isreduced). Overclad regions 507 may further provide mechanical stabilityfor device 500.

FIG. 6 is a block diagram of a simplified optical system utilizing anembodiment of the invention. System 600 includes transmitter 601 andreceiver 602. Transmitter 601 includes light source 610 and light sourcecontroller 620. In the illustrated embodiment, light source 620 is alaser utilizing a hybrid active gain structure, wherein the structurecomprises any embodiment of the invention described above. Light sourcecontroller 620 may control the hybrid active gain structure of lightsource 610 (i.e., light source controller 620 may create an electricaldifference at electrical contacts of light source 610). In oneembodiment, light source controller 620 comprises silicon circuitrywhile light source 610 comprises III-V and silicon semiconductormaterial. Light source 610 may transmit optical signals to modulator 630via any transmission medium known in the art.

The structure of modulator 630 may comprise any embodiment of theinvention described above. Modulator 630 may perform either amplitude orphase modulation of the light received from light source 610. In oneembodiment, optical waveguides of modulator 630 are controlled bymodulator controller 640 (i.e., modulator controller 640 may create anelectrical difference at electrical contacts of modulator 630). Themodulated output of modulator 630 may be transmitted to receiver 602 viaany transmission medium known in the art. Receiver 602 may include anoptical device wherein the structure of said device comprises anyembodiment of the invention described above.

In one embodiment, system 600 is included in a single device or chip,wherein silicon components of system 600 are included on a siliconportion of the chip, and III-V semiconductor components of system 600are included on a III-V portion of the chip. These portions may befabricated independently and subsequently bonded via any bonding processknown in the art.

Reference throughout the foregoing specification to “one embodiment” or“an embodiment” means that a particular feature, structure orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the present invention. Thus, appearancesof the phrases “in one embodiment” or “in an embodiment” in variousplaces throughout the specification are not necessarily all referring tothe same embodiment. Furthermore, the particular features, structures orcharacteristics may be combined in any suitable manner in one or moreembodiments. In addition, it is appreciated that the figures providedare for explanation purposes to persons ordinarily skilled in the artand that the drawings are not necessarily drawn to scale. It is to beunderstood that the various regions, layers and structures of figuresmay vary in size and dimensions.

In the foregoing detailed description, the method and apparatus of thepresent invention have been described with reference to specificexemplary embodiments thereof. It will, however, be evident that variousmodifications and changes may be made thereto without departing from thebroader spirit and scope of the present invention. The presentspecification and figures are accordingly to be regarded as illustrativerather than restrictive.

1. An apparatus comprising: a first semiconductor slab comprising asilicon material and including a first vertical boundary; a secondsemiconductor slab above the first semiconductor slab comprising a III-Vmaterial and including a ridge; at least one overclad region coupled tothe ridge of the second semiconductor slab; and an optical waveguideincluded in the first and second semiconductor slab and formed, at leastin part, by the ridge, the first vertical boundary and the overcladregion(s) to vertically confine an optical mode of the opticalwaveguide, the ridge to laterally confine the optical mode.
 2. Theapparatus of claim 1, further comprising an n-type electrical contactcoupled to the second semiconductor slab; and a p-type electricalcontact coupled to the second semiconductor slab; wherein the secondsemiconductor slab further comprises: a p-type layer including the ridgeand coupled to the p-type electrical contact; an n-type layer coupled tothe first semiconductor slab and the n-type electrical contact; and anactive layer disposed between the n-type layer and the p-type layer. 3.The apparatus of claim 1, further comprising an n-type electricalcontact coupled to the second semiconductor slab; and a p-typeelectrical contact coupled to the second semiconductor slab; wherein thesecond semiconductor slab further comprises: an n-type layer includingthe ridge and coupled to the n-type electrical contact; a p-type layercoupled to the first semiconductor slab and the p-type electricalcontact; and an active layer disposed between the p-type layer and then-type layer.
 4. The apparatus of claim 1, wherein the secondsemiconductor slab further comprises: a first n-type layer including theridge; a second n-type layer coupled to the first semiconductor slab;and an active layer disposed between the first and second n-type layers,the active layer including a tunnel junction to convert n-type majoritycarriers of one of the n-type layers to p-type majority carriers.
 5. Theapparatus of claim 1, further comprising an n-type electrical contactcoupled to the first semiconductor slab; and a p-type electrical contactcoupled to the second semiconductor slab; wherein the first and secondsemiconductor slabs are coupled via a conductive bonding layer, and thesecond semiconductor slab further comprises: a p-type layer includingthe ridge and coupled to the p-type electrical contact; an n-type layercoupled to the conductive bonding layer, and an active layer disposedbetween the n-type layer and the p-type layer.
 6. The apparatus of claim1, further comprising a silicon substrate layer below the firstsemiconductor slab, wherein the first vertical boundary comprises afirst vertical confinement layer disposed between the firstsemiconductor slab and the silicon substrate layer.
 7. The apparatus ofclaim 6, wherein the first vertical confinement layer comprises amaterial with a lower refractive index than silicon.
 8. The apparatus ofclaim 2, the ridge further included in the active layer and to extend tothe n-type layer.
 9. The apparatus of claim 5, the ridge furtherincluded in the active layer and the n-type layer and to extend to theconductive bonding layer.
 10. A system comprising: a light source; amodulator to receive light from the light source; and a transmissionmedium to operatively couple the light source and the modulator; whereinat least one of the light source and the modulator includes an opticaldevice comprising a first semiconductor slab comprising a siliconmaterial and including a first vertical boundary, a second semiconductorslab above the first semiconductor slab comprising a III-V material andincluding a ridge, and an optical waveguide included in the first andsecond semiconductor slab and formed, at least in part, by the ridge,the first vertical boundary to vertically confine an optical mode of theoptical waveguide, the ridge to laterally confine the optical mode. 11.The system of claim 10, the optical device further comprising an n-typeelectrical contact coupled to the second semiconductor slab; and ap-type electrical contact coupled to the second semiconductor slab;wherein the second semiconductor slab further comprises: a p-type layerincluding the ridge and coupled to the p-type electrical contact; ann-type layer coupled to the first semiconductor slab and the n-typeelectrical contact; and an active layer disposed between the n-typelayer and the p-type layer.
 12. The system of claim 10, the opticaldevice further comprising an n-type electrical contact coupled to thesecond semiconductor slab; and a p-type electrical contact coupled tothe second semiconductor slab; wherein the second semiconductor slabfurther comprises: an n-type layer including the ridge and coupled tothe n-type electrical contact; a p-type layer coupled to the firstsemiconductor slab and the p-type electrical contact; and an activelayer disposed between the p-type layer and the n-type layer.
 13. Thesystem of claim 10, wherein the second semiconductor slab of the opticaldevice further comprises: a first n-type layer including the ridge; asecond n-type layer coupled to the first semiconductor slab; and anactive layer disposed between the first and second n-type layers, theactive layer including a tunnel junction to convert n-type majoritycarriers of one of the n-type layers to p-type majority carriers. 14.The system of claim 10, the optical device further comprising an n-typeelectrical contact coupled to the first semiconductor slab; and a p-typeelectrical contact coupled to the second semiconductor slab; wherein thefirst and second semiconductor slabs are coupled via a conductivebonding layer, and the second semiconductor slab further comprises: ap-type layer including the ridge and coupled to the p-type electricalcontact; an n-type layer coupled to the conductive bonding layer, and anactive layer disposed between the n-type layer and the p-type layer. 15.The system of claim 10, the optical device further comprising a siliconsubstrate layer below the first semiconductor slab, wherein the firstvertical boundary comprises a first vertical confinement layer disposedbetween the first semiconductor slab and the silicon substrate layer.16. The system of claim 15, wherein the first vertical confinement layercomprises a material with a lower refractive index than silicon.
 17. Thesystem of claim 12, the ridge of the optical device further included inthe active layer and to extend to the n-type layer.
 18. The system ofclaim 14, the ridge of the optical device further included in the activelayer and the n-type layer and to extend to the conductive bondinglayer.